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Volume 17, Issue 2June 2024
Editor:
  • Deming Chen
Publisher:
  • Association for Computing Machinery
  • New York
  • NY
  • United States
ISSN:1936-7406
EISSN:1936-7414
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SECTION: FPL 2022
introduction
Free
Introduction to the Special Issue on FPL 2022
Article No.: 19, Pages 1–3https://doi.org/10.1145/3643474
research-article
XVDPU: A High-Performance CNN Accelerator on the Versal Platform Powered by the AI Engine
Article No.: 20, Pages 1–24https://doi.org/10.1145/3617836

Today, convolutional neural networks (CNNs) are widely used in computer vision applications. However, the trends of higher accuracy and higher resolution generate larger networks. The requirements of computation or I/O are the key bottlenecks. In this ...

research-article
Open Access
ExHiPR: Extended High-Level Partial Reconfiguration for Fast Incremental FPGA Compilation
Article No.: 21, Pages 1–28https://doi.org/10.1145/3617837

Partial Reconfiguration (PR) is a key technique in the application design on modern FPGAs. However, current PR tools heavily rely on the developer to manually conduct PR module definition, floorplanning, and flow control at a low level. The existing PR ...

research-article
Open Access
GraphScale: Scalable Processing on FPGAs for HBM and Large Graphs
Article No.: 22, Pages 1–23https://doi.org/10.1145/3616497

Recent advances in graph processing on FPGAs promise to alleviate performance bottlenecks with irregular memory access patterns. Such bottlenecks challenge performance for a growing number of important application areas like machine learning and data ...

research-article
The Open-source DeLiBA2 Hardware/Software Framework for Distributed Storage Accelerators
Article No.: 23, Pages 1–32https://doi.org/10.1145/3624482

With the trend towards ever larger “big data” applications, many of the gains achievable by using specialized compute accelerators become diminished due to the growing I/O overheads. While there have been several research efforts into computational ...

research-article
Design, Calibration, and Evaluation of Real-time Waveform Matching on an FPGA-based Digitizer at 10 GS/s
Article No.: 24, Pages 1–28https://doi.org/10.1145/3635719

Digitizing side-channel signals at high sampling rates produces huge amounts of data, while side-channel analysis techniques only need those specific trace segments containing Cryptographic Operations (COs). For detecting these segments, waveform-matching ...

SECTION: FPT 2023 JT
research-article
HyBNN: Quantifying and Optimizing Hardware Efficiency of Binary Neural Networks
Article No.: 25, Pages 1–24https://doi.org/10.1145/3631610

Binary neural network (BNN), where both the weight and the activation values are represented with one bit, provides an attractive alternative to deploy highly efficient deep learning inference on resource-constrained edge devices. However, our ...

research-article
Open Access
On the Malicious Potential of Xilinx’s Internal Configuration Access Port (ICAP)
Article No.: 26, Pages 1–28https://doi.org/10.1145/3633204

Field Programmable Gate Arrays (FPGAs) have become increasingly popular in computing platforms. With recent advances in bitstream format reverse engineering, the scientific community has widely explored static FPGA security threats. For example, it is now ...

research-article
Open Access
Covert-channels in FPGA-enabled SmartSSDs
Article No.: 27, Pages 1–23https://doi.org/10.1145/3635312

Cloud computing providers today offer access to a variety of devices, which users can rent and access remotely in a shared setting. Among these devices are SmartSSDs, which are solid-state disks (SSD) augmented with an FPGA, enabling users to instantiate ...

research-article
Open Access
Across Time and Space: Senju’s Approach for Scaling Iterative Stencil Loop Accelerators on Single and Multiple FPGAs
Article No.: 28, Pages 1–33https://doi.org/10.1145/3634920

Stencil-based applications play an essential role in high-performance systems as they occur in numerous computational areas, such as partial differential equation solving. In this context, Iterative Stencil Loops (ISLs) represent a prominent and well-...

research-article
AEKA: FPGA Implementation of Area-Efficient Karatsuba Accelerator for Ring-Binary-LWE-Based Lightweight PQC
Article No.: 29, Pages 1–23https://doi.org/10.1145/3637215

Lightweight PQC-related research and development have gradually gained attention from the research community recently. Ring-Binary-Learning-with-Errors (RBLWE)-based encryption scheme (RBLWE-ENC), a promising lightweight PQC based on small parameter sets ...

SECTION: Original Articles
research-article
Open Access
High-efficiency Compressor Trees for Latest AMD FPGAs
Article No.: 30, Pages 1–32https://doi.org/10.1145/3645097

High-fan-in dot product computations are ubiquitous in highly relevant application domains, such as signal processing and machine learning. Particularly, the diverse set of data formats used in machine learning poses a challenge for flexible efficient ...

research-article
AxOMaP: Designing FPGA-based Approximate Arithmetic Operators using Mathematical Programming
Article No.: 31, Pages 1–28https://doi.org/10.1145/3648694

With the increasing application of machine learning (ML) algorithms in embedded systems, there is a rising necessity to design low-cost computer arithmetic for these resource-constrained systems. As a result, emerging models of computation, such as ...

research-article
Open Access
ScalaBFS2: A High-performance BFS Accelerator on an HBM-enhanced FPGA Chip
Article No.: 32, Pages 1–39https://doi.org/10.1145/3650037

The introduction of High Bandwidth Memory (HBM) to the FPGA chip makes it possible for an FPGA-based accelerator to leverage the huge memory bandwidth of HBM to improve its performance when implementing a specific algorithm, which is especially true for ...

research-article
Designing an IEEE-Compliant FPU that Supports Configurable Precision for Soft Processors
Article No.: 33, Pages 1–32https://doi.org/10.1145/3650036

Field Programmable Gate Arrays (FPGAs) are commonly used to accelerate floating-point (FP) applications. Although researchers have extensively studied FPGA FP implementations, existing work has largely focused on standalone operators and frequency-...

research-article
Open Access
R-Blocks: an Energy-Efficient, Flexible, and Programmable CGRA
Article No.: 34, Pages 1–34https://doi.org/10.1145/3656642

Emerging data-driven applications in the embedded, e-Health, and internet of things (IoT) domain require complex on-device signal analysis and data reduction to maximize energy efficiency on these energy-constrained devices. Coarse-grained reconfigurable ...

research-article
HierCGRA: A Novel Framework for Large-scale CGRA with Hierarchical Modeling and Automated Design Space Exploration
Article No.: 35, Pages 1–31https://doi.org/10.1145/3656176

Coarse-grained reconfigurable arrays (CGRAs) are promising design choices in computation-intensive domains, since they can strike a balance between energy efficiency and flexibility. A typical CGRA comprises processing elements (PEs) that can execute ...

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