Survey of Machine Learning for Software-assisted Hardware Design Verification: Past, Present, and Prospect
With the ever-increasing hardware design complexity comes the realization that efforts required for hardware verification increase at an even faster rate. Driven by the push from the desired verification productivity boost and the pull from leap-ahead ...
CuPBoP: Making CUDA a Portable Language
CUDA is designed specifically for NVIDIA GPUs and is not compatible with non-NVIDIA devices. Enabling CUDA execution on alternative backends could greatly benefit the hardware community by fostering a more diverse software ecosystem.
To address the need ...
Load Balanced PIM-Based Graph Processing
Graph processing is widely used for many modern applications, such as social networks, recommendation systems, and knowledge graphs. However, processing large-scale graphs on traditional Von Neumann architectures is challenging due to the irregular graph ...
Modeling Retention Errors of 3D NAND Flash for Optimizing Data Placement
Considering 3D NAND flash has a new property of process variation (PV), which causes different raw bit error rates (RBER) among different layers of the flash block. This article builds a mathematical model for estimating the retention errors of flash ...
Capacity-Aware Wash Optimization with Dynamic Fluid Scheduling and Channel Storage for Continuous-Flow Microfluidic Biochips
Continuous-flow microfluidic biochips are gaining increasing attention with promising applications for automatically executing various laboratory procedures in biology and biochemistry. Biochips with distributed channel-storage architectures enable each ...
Enhanced Watermarking for Paper-Based Digital Microfluidic Biochips
Paper-based digital microfluidic biochip (PB-DMFB) technology provides a promising solution to many biochemical applications. However, the PB-DMFB manufacturing process may suffer from potential security threats. For example, a Trojan insertion attack may ...
A Scenario-Based DVFS-Aware Hybrid Application Mapping Methodology for MPSoCs
Sound techniques for mapping soft real-time applications to resources are indispensable for meeting the application deadlines and minimizing objectives such as energy consumption, particularly on heterogeneous MPSoC architectures. For applications with ...
Semi-Permanent Stuck-At Fault injection attacks on Elephant and GIFT lightweight ciphers
Fault attacks pose a potent threat to modern cryptographic implementations, particularly those used in physically approachable embedded devices in IoT environments. Information security in such resource-constrained devices is ensured using lightweight ...
A Single Bitline Highly Stable, Low Power With High Speed Half-Select Disturb Free 11T SRAM Cell
A half-select disturb-free 11T (HF11T) static random access memory (SRAM) cell with low power, better stability and high speed is presented in this paper. The proposed SRAM cell works well with bit-interleaving design, which enhances soft-error immunity. ...
An Open-Source ML-Based Full-Stack Optimization Framework for Machine Learning Accelerators
- Hadi Esmaeilzadeh,
- Soroush Ghodrati,
- Andrew Kahng,
- Joon Kyung Kim,
- Sean Kinzer,
- Sayak Kundu,
- Rohan Mahapatra,
- Susmita Dey Manasi,
- Sachin Sapatnekar,
- Zhiang Wang,
- Ziqing Zeng
Parameterizable machine learning (ML) accelerators are the product of recent breakthroughs in ML. To fully enable their design space exploration (DSE), we propose a physical-design-driven, learning-based prediction framework for hardware-accelerated deep ...
Applying reinforcement learning to learn best net to rip and re-route in global routing
- Upma Gandhi,
- Erfan Aghaeekiasaraee,
- Sahir,
- Payam Mousavi,
- Ismail S. K. Bustany,
- Mathew E. Taylor,
- Laleh Behjat
Physical designers typically employ heuristics to solve challenging problems in global routing. However, these heuristic solutions are not adaptable to the ever-changing fabrication demands, and the experience and creativity of designers can limit their ...
A Cost-Driven Chip Partitioning Method for Heterogeneous 3D Integration
Three-dimensional integration circuit (3D IC) offers significant benefits in terms of performance and cost. Existing research in through-silicon via (TSV)-based 3D IC partitioning has focused on minimizing the number of TSVs to reduce costs. Partitioning ...
Removal of SAT-Hard Instances in Logic Obfuscation Through Inference of Functionality
Logic obfuscation is a prominent approach to protect intellectual property within integrated circuits during fabrication. Many attacks on logic locking have been proposed, particularly in the Boolean satifiability (SAT) attack family, leading to the ...
